[isabelle] CFP DATE15 - Formal Methods and System Verification
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- Subject: [isabelle] CFP DATE15 - Formal Methods and System Verification
- From: "Schmaltz, J." <j.schmaltz at tue.nl>
- Date: Wed, 6 Aug 2014 07:01:59 +0000
- Accept-language: en-US
- Thread-index: AQHPsURRGMD9qHk3w0qkvWG2/oIsgA==
- Thread-topic: CFP DATE15 - Formal Methods and System Verification
******************* DATE 15 Call for Papers – D4 Topic Formal Methods and System Verification ******************
Design Methods and Tools Track @ DATE 2015
Grenoble, France - March 9-13, 2015
Submission by Sunday September 14, 2014, 23:59:59 CET
Notification of Acceptance November 07, 2014
The Design, Automation and Test in Europe conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. The Design Methods and Tools Track is devoted to design automation and design tools for electronic and embedded systems. Emphasis is on methods and tools related to the use of computers in designing products. This includes designer feedback on existing design methods and tools as well as to initiate discussions on requirements of future system architectures, design flows and environments The Formal Methods and System Verification topic (D4) is one of the thirteen topics foreseen in the Design Methods and Tools Track.
This five-day event consists of a conference with plenary keynotes, regular papers, interactive presentations, panels and hot-topic sessions, tutorials, master courses and workshops. The scientific conference is complemented by a commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services. Both the conference and the exhibition, together with the many user group meetings, fringe meetings, university booth and social events offer a wide variety of opportunities to meet and exchange information.
The Formal Methods and System Verification Track (D4) is devoted to the presentation and discussion of state-of-the-art advances in the theory and practice of formal verification methods. Topics of interest include, but are not limited to:
- Formal verification and specification techniques including equivalence checking, model checking, symbolic simulation, theorem-proving, abstraction and refinement techniques, and real time verification.
- Technologies supporting formal verification, including SMT, SAT, BDD, ATPG, and related work.
- Applications of formal and semi-formal techniques to verify functional and non-functional aspects of hardware and software systems. This includes practical applications and case-studies about verification of IPs, SoCs, cores and real-time/embedded systems.
- Verification in practice, namely the integration of verification into the design flow.
- Applications of formal and semi-formal techniques into new and challenging areas, like multi-core and parallel architectures,
asynchronous designs, analog and mixed-signal designs, power modelling and analysis, hardware and software security, etc.
TOPIC TECHNICAL COMMITTEE
Jason Baumgartner, IBM Corporation (chair) Armin Biere, Universitaet Linz
Per Bjesse, Synopsys Gianpiero Cabodi, Politecnico di Torino
Alessandro Cimatti, Fondazione Bruno Kessler Barbara Jobstmann, EPFL, Jasper DA, CNRS/Verimag
Katell Morin-Allory, TIMA Laboratory Julien Schmaltz, Eindhoven University of Technology (co-chair)
Christoph Scholl, Albert-Ludwigs-University Freiburg Daryl Stewart, ARM
All manuscripts must be submitted electronically before Sunday September 14, 2014 23:59:59 CET, following the instructions on the conference Web page:
The accepted file format is PDF. Any other format and manuscripts received in hard-copy form will not be processed.
Papers can be submitted for either formal oral presentation or for interactive presentation. Oral presentations require novel and complete research work supported by experimental results. Interactive presentations are expected to articulate emerging and future design, verification and test problems including work in progress and identify open problems that merit innovative future research. These presentations are given on a laptop in a face-to-face discussion area.
Submissions should not exceed 6 pages in length for oral-presentation papers and 4 pages in length for interactive-presentation papers, and should be formatted as close as possible to the final format: A4 or letter sheets, double column, single spaced, Times or equivalent font of minimum 10pt (templates are available on the DATE Web site for your convenience). To permit blind review, submissions should not include the author names. Any submission not in line with the above rules will be discarded.
All papers will be evaluated with regard to their suitability for the conference, originality, and technical soundness. The Programme Committee reserves the right to reorient oral-presentation papers to interactive-presentation and vice versa, to obtain the most suitable presentation format.
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